This invention relates to an amplifier arrangement, comprising:
an input terminal, an output terminal, and first and a second supply terminal for receiving a supply voltage, PA1 a first transistor of a first conductivity type and a second transistor of a second conductivity type, each having a control electrode and a first and a second main electrode, PA1 a driver stage having an input coupled to the input terminal and having first and second outputs coupled to the control electrodes of the first and the second transistors, respectively, PA1 the second main electrodes of the first and the second transistors being coupled to the first and the second supply terminal, respectively, and the first main electrodes of the first and second transistors being coupled to the output terminal. PA1 third and sixth transistors of the second conductivity type, and fourth and fifth transistors of the first conductivity type, each transistor having a control electrode, a first and a second main electrode, PA1 a first current source for supplying a first current, coupled between the first supply terminal and the first output of the driver stage, PA1 a second current source for supplying a second current, coupled between the second output of the driver stage and the second supply terminal, PA1 biasing means for supplying respective bias voltages to the control electrodes of the third, fourth, fifth and sixth transistors, PA1 the second main electrodes of the third and the fourth transistor being coupled to the input of the driver stage, PA1 the first main electrode of the third transistor and the second main electrode of the fifth transistor being coupled to the first output of the driver stage, PA1 the first main electrode of the fourth transistor and the second main electrode of the sixth transistor being coupled to the second output of the driver stage.
Such an amplifier arrangement is known from FIG. 1 of U.S. Pat. No. 4,570,128. The driver stage in the known amplifier arrangement comprises third and fourth transistors coupled anti-parallel between the first and second outputs of the driver stage. The control electrodes of the third and fourth transistors are coupled to respective biasing means. The input of the driver stage is coupled to the second output of the driver stage so that a signal current applied to the input is directly applied to the control electrode of the second transistor. A signal current applied to the input terminal will result in a simultaneous increase or decrease of the potentials on the control electrodes of the first and second output transistors. Due to the simultaneous variation of these potentials, it is possible to drive the control electrode potential of one of the first and second transistors close to the supply terminal voltage, thus effectively turning the transistor off when a large signal current is applied to the input terminal. A drawback of this arrangement is that it takes a finite amount of time to turn the transistor back on when the signal current decreases again. This turn-on time causes distortion, especially during cross-over when the first transistor takes over from the second transistor or vice versa.